| 摘要 |
There is provided an apparatus for detecting a synchronizing signal, including a first circuit for extracting bit clocks from serial data received, a shift register for shifting the serial data bit by bit on the basis of the bit clocks, and latching the thus shifted serial data, a second circuit for counting the bit clocks, and generating word clocks in accordance with the number of count of the bit clocks for outputting parallel data, a third circuit for detecting a synchronization pattern from the serial data stored in the shift register, and generating a first synchronization-detecting signal, a fourth circuit for detecting a synchronization pattern from the parallel data, and generating a second synchronization-detecting signal, and a fifth circuit for determining whether frame synchronization is made, by the first and second synchronization-detecting signals, and generating a frame synchronization indication signal indicative of whether frame synchronization is made or not. The third and fourth circuits are switched in accordance with the frame synchronization indication signal. Even if a wrong synchronization pattern appears in serial data during data is transferred, the above-mentioned apparatus makes it possible to avoid wrong synchronization by judging whether frame synchronization is made or not, and switching the third and fourth circuits in accordance with the judgement.
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