| 摘要 |
A non-volatile semiconductor storage device has a plurality of non-volatile memory cells formed by cell transistors in which a first voltage is applied to a word line through an address selection circuit and a second voltage lower than the first voltage is applied to the transistors through a selection line and/or a bit line. The voltage applied to the transistors is lower than that conventionally employed. Accordingly, a withstand voltage of the transistor can be reduced to decrease the occupied area of the transistors to realize higher integration.
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