| 摘要 |
A shared memory type vector processing system in which CPUs (10a - 10n) are connected by a bus (30) for transferring a vector processing instruction generated from each CPU to each CPU and the respective CPUs are grouped into a master CPU which issues a vector processing instruction to other CPU and slave CPUs operating as a multi-vector pipeline in synchronization with vector processing units (14a - 14n) in the master CPU, the master CPU including a memory access control unit (12) for issuing said vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring said instruction to all the CPUs including its own CPU through a bus, and the master CPU and the slave CPU including a vector processing instruction control unit (13) for comparing issuing source CPU information contained in a vector processing instruction and master CPU information set at its own CPU and conducting instruction issuance based on the vector processing instruction when the information accord with each other and invalidating the vector processing instruction when the information fail to accord with each other. |
