Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing

摘要

Novel overlay targets and an algorithm metrology are provided that minimize the overlay measurement error for fabricating integrated circuits. The method is particularly useful for accurately measuring layer-to-layer overlay on a substrate having material layers, such insulating, polysilicon, and metal layers that have asymmetric profiles over the overlay targets resulting from asymmetric deposition or chemical/mechanically polishing. The novel method involves forming a triangular-shaped first overlay target in a first material layer on a substrate. A second material layer, having the asymmetric profile is formed over the first material layer. During patterning of the second material layer, smaller triangular-shaped second overlay target are etched. The vertices of the smaller second overlay targets are aligned to the midpoints of the sides of the first overlay target, which are less sensitive to the asymmetries in the second material layer. An algorithm is then used to determine the positions of the centroids of the first and second overlay targets, which coincide with perfect alignment. The distance between the two centroids is the degree of layer-to-layer misalignment of the two material layers.