DRAM CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF

摘要

Memory cells each comprise a transistor and a capacitor. A memory node (Sp) of the capacitor is arranged in a first recess (V) while a gate electrode of the transistor is arranged in a second recess. An upper source/drain region (SDo), a channel region (KA) and a lower source/drain region (SDu) of the transistor are arranged one above the other and each abut against a first flank (Fa). The first flank (Fa) is provided with a capacitor dielectric (Ka, Kb) which comprises a cavity in the area of the lower source/drain region (SDu) in which the memory node (Sp) abuts against the lower source/drain region (SDu). The second recess of a first set of memory cells can abut against the memory node (Sp) which is arranged in the first recess (V) of a second set of memory cells. The second recesses can be parts of word line trenches (GW) which run in a transversal manner in relation to insulation trenches. Above the cavity, preferably one insulating structure (Ia) is arranged in the first recess (V) which abuts against two of the insulation trenches which are adjacent to one another. Bit lines (B) contact the upper source/drain region (SDo) by means of contacts (K).