发明名称 ONE-TO-MULTIPLE BUS BRIDGE BY MULTIPLE-LOGIC FIFO
摘要 PROBLEM TO BE SOLVED: To use FIFO storage capacity so that bandwidth efficiency is improved and a circuit is reduced in size and cost by providing a multiple-logic FIFO system wherein a 1st and a 2nd logic FIFO share a common storage device. SOLUTION: A demultiplexer and a control circuit enqueues cycle information addressed to a 1st I/O interface 1312 from a cycle information output 1323 to a 1st logic FIFO according to a data preparation completed output 1326. According to a 1st I/O interface usable output 1329, the information is dequeued from the 1st logic FIFO to the 1st I/O bus interface 1312. Then cycle information addressed to a 2nd I/O interface 1314 is enqueued from the cycle information output 1323 to a 2nd logic FIFO according to the data preparation completed output 1326. According to the 2nd I/O interface usable output 1329, the information is dequeued from the 2nd logic FIFO to the 2nd I/O bus interface 1314.
申请公布号 JP2000155740(A) 申请公布日期 2000.06.06
申请号 JP19990295161 申请日期 1999.10.18
申请人 HEWLETT PACKARD CO <HP> 发明人 DERRICK A SHERLOCK
分类号 G06F13/36;G06F5/14;G06F13/38;G06F13/40;(IPC1-7):G06F13/38;G06F5/06 主分类号 G06F13/36
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