WORD LINE DECODING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A word line decoding circuit is provided to attain high speed decoding operation without a loss in a layout area. CONSTITUTION: A word line decoding circuit includes a buffer section(10) having a plurality of buffers(B1-Bi), a first decoding section(20) having a plurality of first decoders(PD1-PDs), and a second decoding section(40) having a plurality of second decoders (MD1-MDk). The buffers(B1-Bi) temporarily store and output plural address signals(A1-Ai). The first decoders (PD1-PDs) pre decode the address signals(A1-Ai) offered from the buffers(B1-Bi). The second decoders(MD1-MDk) decode the output signals from the first decoders(PD1-PDs) and generate signals to activate word lines(WL1-WLk) when a control transistor(CT) operates in response to a pulse control signal(PCS). A source of the control transistor(CT) is grounded and a drain thereof is commonly connected to the second decoders(MD1-MDk). The word line decoding circuit reduces delay time in activating the word lines, so that high speed decoding operation is attained. Further, loss in layout area is prevented since the delay circuit inside the first decoders is not required.