发明名称 Optimal resistor network layout
摘要 A resistor network having a precise ratio of resistances of all resistors within the network while having a compact layout to minimize area is described. The integrated circuit resistor network has a plurality of unit resistors. Each unit resistor is composed of a thin film resistive material. The area of the thin film resistive material to form the unit resistor is a median value of the resistor elements to be formed into said integrated circuit resistor network. Each unit resistor has a contact means to connect to the plurality of unit resistors. A plurality of metal interconnection segments will connect to the contact means to form said integrated circuit resistor network. A plurality of metal conductive segments are connected to a metal interconnection segments and to external circuitry to connect the external circuitry to the integrated circuit resistor network.
申请公布号 US6060760(A) 申请公布日期 2000.05.09
申请号 US19970910269 申请日期 1997.08.13
申请人 TRITECH MICROELECTRONICS, LTD. 发明人 TAN, KIEN BENG
分类号 H01L27/08;(IPC1-7):H01L29/40 主分类号 H01L27/08
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