| 摘要 |
PURPOSE: A power-on reset circuit is provided to easily integrate to the inside of a device chip regardless of a power-on reset time and control the power-on reset time according to a predetermined value of a counter. CONSTITUTION: The power-on reset circuit includes a generator(202), a counter(204) and a compounding logic circuit(206) in a power-on reset circuit for a sequential logic generating a power-on reset signal when a power is applied, and sequential logics are immediately initialized to logic states required. The generator generates a clock signal when the power is applied. The counter generates a counted data with being synchronized to the clock signal. The compounding logic circuit generates the power-on reset signal when the counted data is identical to a data which is previously established. The generator and counter are simultaneously inactivated in response to the power-on reset signal so that the generator is inactivated and an output of the counter is maintained.
|
