| 摘要 |
A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). The data set also includes secondary signal processing circuitry (40) which transmits and receives diagnostic and control information over respective secondary channels of the transmit line and receive lines. The secondary signal processing circuitry is controlled by a secondary controller (50) over a plurality of buses (SA, SC, SD). The secondary controller also includes a microprocessor (510) and associated peripherals (515, 520, 525, 530, 535). The primary and secondary controllers communicate with each other via a bus interface (60).
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