| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit which prevents the supply of unstable clock just after reset cancellation and prevents a malfunction with a simple circuit configuration. SOLUTION: This circuit is provided with a gate circuit 8 which performs pass control of an oscillation signal of a voltage controlled oscillator 4 and a flip-flop 7 which makes an output signal of a phase comparator 1 an clock input and outputs a high signal to the circuit 8 according to the output signal just after lockup. Thus, a state of the time when a frequency is led in does not have to be considered, design with an ideally dumping coefficient is made possible, a transient response characteristics is improved, and also, an only stable output is outputted to an external circuit. |
