| 摘要 |
A data signal baseline error detector for monitoring and detecting undesired shifts in the baseline, or other intermediate level, of a multilevel data signal, such as an MLT3 Ethernet signal, as well as correcting for DC or low frequency offsets within a data receiving system. A signal slicing circuit generates two control signals: a data baseline signal indicates whether the data signal level is above or below a predetermined baseline reference level; and a data zero signal indicates when the data signal is in its zero, i.e., baseline, state and, when asserted, initiates a count sequence by a counter. The count sequence is decoded and the resulting decoded pulse sequence is gated in accordance with the data zero signal. Such pulses can be used to control a sampling circuit for sampling the data baseline signal or, alternatively, for sampling the data signal directly while in its zero state. The gating of the decoded pulses is done in such a manner as to prevent the outputting of decoded pulses which would otherwise occur too closely to the rising or falling edge of the data signal as it transitions away from its zero state, thereby ensuring that any signal sampling done occurs only during the true zero, or baseline, state of the data signal and not during any periods of signal level transitions.
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