发明名称 CIRCUIT HAVING FIFO MEMORY
摘要 PROBLEM TO BE SOLVED: To realize a first-in first-out(FIFO) memory having a multi-port memory accessed for read-out/write-in operation by activating a selected read-out/ write-in word line without using a counter. SOLUTION: The write-in word line is successively activated by a single bit (e.g. bit of '1') to circulate a write-in pointer shift register 204. Relating to a read-out pointer, a coincidence circuit consisting of transistors 207-210 and an inverter 211 looks ahead a row of memory cell, and compares the present position of the read-out pointer with the present position of the write-in pointer. When they agree, it shows that the read-out pointer advances to the row (m-1) adjacent to the row of the write-in pointer (m), and thus, the line 216 transits from high (high potential) to low (low potential), and this transition is conducted to an output latch circuit 217, and an empty flag EF is set.
申请公布号 JP2000082282(A) 申请公布日期 2000.03.21
申请号 JP19990258737 申请日期 1999.09.13
申请人 AT & T CORP 发明人 FENSTERMAKER LARRY R;O'CONNOR KEVIN J
分类号 G06F5/14;G06F5/10;G11C7/00;G11C8/16 主分类号 G06F5/14
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