| 摘要 |
Semiconductor memory device with an on-chip error correction circuit (ECC) capable of correcting at least two erroneous bits in the data bits corresponding to an input/output memory block, and with improved access time. Memory cell array 100 is divided into a number of I/O memory blocks IOMB, each block having a corresponding input/output circuit 220 and storing a plurality of data and check bits, being equally divided into at least two groups, e.g. odd and even bits. For each block, and an error correction circuit arrangement, 200_bottom, 200_top, corrects first and second errors in the data bits of the first and second groups respectively. During a first cycle of a read mode of operation, the circuits 200 receive, in parallel, odd and even-numbered data and check bits and generate first and second syndrome bits. During a second cycle, errors in the odd and even-numbered data bits are corrected in response to the syndrome bits, either using two error detectors and correctors in parallel (Fig. 6), or a single error detector and corrector connected to both syndrome generators (Figs. 12 and 13). |
