发明名称 MOS MULTIPLIER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain an MOS multiplier circuit which can be formed on a semiconductor integrated circuit by connecting plural quadritail cells in the state of arranging their output pair reverse to each other. SOLUTION: Transistors M1 to M4 constitute a first quadritail cell and transistors M5 to M8 constitute a second quadritail cell to constitute a multiplier cell. The two quadritail cells whose outputs are cross-connected are driven by the differential output current of a MOS differential pair respectively consisting of transistors M13 and M14. When an input voltage VY is a non- signal, both of the output current of the first quadritail cell and that of the second quadritail cell are linear with respect to the input voltage VX. Since a multiplier cell consists of the two quadritail cell whose outputs are cross- connected, the MOS multiplier circuit which can constitute the multiplier cell and a required input circuit of only N-channel transistor is realized.
申请公布号 JP2000048112(A) 申请公布日期 2000.02.18
申请号 JP19980217324 申请日期 1998.07.31
申请人 NEC CORP 发明人 KIMURA KATSUHARU
分类号 G06G7/163;H03D7/12;H03D7/14;(IPC1-7):G06G7/163 主分类号 G06G7/163
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