System for information processing comprising plurality of processors where interconnection nodes insure priority access to corresponding addressable spaces and establish hierarchy of processor priority access

摘要

In this device, each processor (P1 to P3) is associated with at least one addressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC). Between all the processors and each addressable space is connected an intercommunicating connection node (N1 to N3), each connection node including control means (LC, D1, D2) for ensuring priority of access of any processor to its own addressable space; and ensuring a hierarchy of priority of access to the addressable spaces of the other processors among said plurality of processors.