发明名称 METHOD AND SYSTEM FOR FETCHING DISCONTINUOUS INSTRUCTION IN SINGLE CLOCK CYCLE
摘要 PROBLEM TO BE SOLVED: To obtain a system for taking discontinuous blocks of instructions in a data processing system by allowing an auxiliary cache means to overlay 2nd instructions, when 1st instructions are branches to the 2nd instructions. SOLUTION: When 1st instructions have the branches to 2nd instructions, the auxiliary cache means overlays the 2nd instructions. In this system, a branch history table(BHT) 104 receives a BHT update signal and outputs a read signal. The read signal from the BHT 104 is supplied to a branching logic 116. An instruction cache 106 receives a write signal from an external supply source, such as an L2 cache. The instruction cache 106 outputs 8 instructions to the branching logic 116. An address-0 signal is supplied directly to the branching logic 116. The branching logic 116 supplies an override address signal to a multiplexer 120.
申请公布号 JP2000029701(A) 申请公布日期 2000.01.28
申请号 JP19990119906 申请日期 1999.04.27
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 MCDONALD ROBERT GREG
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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