| 摘要 |
A phase locked delay circuit which reduces the layout area of a semiconductor device includes a delay buffer, a main delay portion, a delay line, means for detecting phase synchronization, a switching unit, a clock driver, and a flag signal generator. The delay buffer receives an external system clock signal, delays the received signal for a predetermined first delay time, and buffers the delayed signal. The main delay portion delays the output of the delay buffer for a predetermined second delay time in response to a flag signal, or bypasses the output of the delay buffer. The delay line sequentially delays the output of the main delay portion for a unit time. The phase synchronization detecting means detects a third delay time required for synchronizing the output of the main delay portion with the output of the delay buffer in response to the flag signal, using the output of the delay line, and activates a corresponding enable signal. The flag signal generator activates the flag signal only when the phase synchronization detecting means detects the third delay time. The switching unit is controlled by enable signals and switches a corresponding signal among signals output by the delay line. The clock driver delays the output of the switching for a fourth delay time and outputs the delayed signal as an internal clock signal.
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