| 摘要 |
A frequency synthesizer generates, through setting of a frequency control value, a reference clock having a frequency necessary to read data from a medium. When reading data from an arbitrary position on the medium, a setting control unit sets in the frequency synthesizer a frequency control value corresponding to the zone position, thereby allowing the frequency synthesizer to control a reference clock frequency, and sets in a single or a plurality of processing units other than the frequency synthesizer a predetermined control value corresponding to the read position on the medium. A settling wait processing unit calculates a settling time T1 required for a frequency of the frequency synthesizer to become stable and a setting processing time T2 necessary for the setting control of the other processing unit, and defines as a wait time Tw a difference (T1-T2) between the settling time T1 and the setting processing time T2, during which wait time Tw a migration to the subsequent processing is kept waiting.
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