| 摘要 |
<p>1,261,749. Digital transmission systems. HEWLETT PACKARD Ltd: 10 June,. 1969, No. 29447/69. Heading H4P. A test signal of known pattern is generated and applied to a channel the output from which is compared with a similar signal generated at the receiving end. The test signals are derived from shift. register generators which may generate pseudo-random signals or predetermined words which recirculate indefinitely. A feed forward shift register differentiates between synchroniza tion loss and error bursts. A test sequence is produced in synchronism. with a clock 17 by using a shift register 19 connectible as a pseudo-random or predetermined word generator. The receiver has a similar generator 21 with the facility that a signal on line 23 causes generator 21 to synchronize onto the received data. Generator 21 may be triggered by a clock extraction circuit 22 if a local clock is not available. Generator 21 output is compared at 25 with the received sequence and fed to a display 27. The comparator 25; output is also fed to, a. shift register in a synchronization loss detector 29 which distinguishes between loss of synchronism, which gives a signal on line 23, and errors. A violation detector 31 detects whether a sequence is being properly generated. Gating circuits (not shown) may be included to prevent a display of error information if there is a loss of synchronism. The shift register generators may comprise a series of programmable flip-flops (33-41) connected to receive, on one input; clock pulses and on another input either the output of the preceding flip-flop or the mod 2 sum of the precoding flip-flop plus the output of the last flip-flop (41) (see Fig. 3, not shown). Alternatively a similar feedback register (48), see Fig. 5 (not shown), may be coupled to a feed forward register (50) so that after six clock pulses the contents of the registers will be identical. In Fig. 7. (not shown) a local generator 53 isswitohable to a feed forward or feed back mode: In position (2) of switch (55) the shift registers in transmitter and receiver act identically to produce a desired error information at the output of a non-equivalence gate (57). With switch (55) in position (1) synchronization will takeplace. In Fig. 8 (not shown) a shift register (59) is connected to recognize the sequence of errors caused by loss of synchronization.</p> |
