发明名称 VARIABLE DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a variable delay circuit which can supply reference signals whose phases can be controlled independently without narrowing down a range of phase shifting and without increasing minimum units of phase adjustment and is small in circuit scale. SOLUTION: Delay circuit arrays 101, and 106 to 109 are provided which are different in phase adjustment range. An external signal is inputted to the 1st delay circuit array 101, the 2nd delay circuit arrays 106 to 109 select switches in switch arrays 102 to 105 specified with control signals 151 to 155 from terminals provided repeatedly to the 1st delay circuit array 101 corresponding to respective phase-adjustable ranges, and a delayed reference input signal is inputted to the 2nd delay circuits 106 to 109 independently. The 2nd delay circuit arrays 106 to 109 further delay the delayed cycle input signal. Arbitrary delay can be given the sum of the number of unit delay elements D passed through in the 1st delay circuit array 101 and the number of unit delay elements D passed through in the 2nd delay circuit arrays 106 to 109.
申请公布号 JPH11261388(A) 申请公布日期 1999.09.24
申请号 JP19980061055 申请日期 1998.03.12
申请人 HITACHI LTD 发明人 SATO TAKASHI;NISHIO YOJI;NAKAGOME YOSHINOBU
分类号 G11C11/4076;H03K5/13;H03K5/131;H03K5/15;H03L7/00 主分类号 G11C11/4076
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