| 摘要 |
A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors, MAP (120), in the memory subsystem (160-16n). The MAP may comprise one or more field programmable gate arrays, FPGA (134), which function to perform identified algorithms in conjunction with, and tightly coupled to a microprocessor (120-12n) and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit (132) within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory, ROM (182), located adjacent to the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system configuration time. A computer system structure MAP disclosed herein may function in normal or direct memory access, DMA, modes of operation and in the later mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of the user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of the user applications containing algorithms that can be executed in the programmable hardware.
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