| 摘要 |
PROBLEM TO BE SOLVED: To make realizable a plurality of circuits regarding the evaluation of a computer architecture without lowering the processing capability by performing the arithmetic processing of a specified multiplying circuit. SOLUTION: The constituent bits (32 bits) constituting a multiplier are divided into two-bit parts, which are multiplied by 0, 1, 2, and 3. When the multiplicant is multiplied by '3', the value obtained by multiplying the multiplicand by -1 is outputted and at the same time, 1 is added to a partial term where the multiplicand is multiplied by a high-order partial product (the number obtained by multiplying the partial product by '4' is handled). Thus, the value obtained by multiplying the multiplicand by '-1' is outputted and at the same time, 1 is added to the partial term where the multiplicand is multiplied by the high- order partial product, so that the value obtained by multiplying the multiplicand by '1' is subtracted from the value obtained by multiplying the multiplicand by '4'. Consequently, the result of the multiplication of the multiplicand by '3' can be obtained. Consequently, logic array blocks needed for the operation can be reduced. |
