DYNAMIC CLOCK GENERATION CIRCUIT FOR SYNCHRONOUS DRAM

摘要

PROBLEM TO BE SOLVED: To minimize a delay amount for a system clock by generating an auto-pulse type internal clock holding the high state of the internal clock only for a set section in response to a disable signal. SOLUTION: An enable pass part 100 generates second transition of an internal clock PCLK rapidly following to the second transition (low→high) in response to first transition (high→low) of a clock outputted from an input buffer 10. A disable pass part 200 receives the output of the input buffer 10 also, and supplies a first disable signal H and a second disable signal I to the enable pass part 100 delayed by a time set by inverters 30, 31. The enable pass part 100 becomes a low state after holding the high state of the internal clock only for the set section in response to the first, second disable signals, and then, the enable pass part 100 outputs the internal clock of a high section relatively shorter than a low section.