LAYOUT PATTERNING DEVICE OF SECICONDUCTOR INTEGRATED CIRCUIT,申请号JP19970229456-传众专利搜索

首页产品黄页商标征信

会员服务注册登录

法人/股东/高管

发明名称	LAYOUT PATTERNING DEVICE OF SECICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号	JPH1167926(A)	申请公布日期	1999.03.09
申请号	JP19970229456	申请日期	1997.08.26
申请人	NEC CORP	发明人	YAMAGUCHI MASAYA
分类号	H01L21/82;G06F17/50;(IPC1-7):H01L21/82	主分类号	H01L21/82
代理机构		代理人
主权项
地址

您可能感兴趣的专利

Quinazoline compounds and their use in perfume compositions

Methods of forming activated carbons

Nanocatalysts structure, process for the preparation and use thereof

Area efficient through-hole connections

Method and structure of forming backside through silicon via connections

Integrated circuit packaging system with interconnects and method of manufacture thereof

Method for conductivity control of (Al,In,Ga,B)N

Method for manufacturing and reoxidizing a TiN/Ta2O5/TiN capacitor

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

Semiconductor device and fabrication method

Integrated circuit packaging system with an encapsulation and method of manufacture thereof

Manufacturing method for semiconductor device carrier and semiconductor package using the same

Fabrication method of packaging substrate having through-holed interposer embedded therein

Method for manufacturing photoelectric conversion device

Deposition apparatus and method for manufacturing organic light emitting diode display using the same

Method for the analysis of solid objects

Polypeptide microparticles

Flow cytometer method and apparatus

Concentration measuring apparatus for hydrogen sulfide in gas flow, and method for determining sulfide ion

Accordion bioreactor