| 摘要 |
<p>Conventional methods of manufacturing semiconductor devices are such that semiconductor devices are insufficient in flattening, great in surface step difference, and liable to cause wiring disconnections in the case of multilayer interconnection, causing reduction in yield. Also, with the conventional methods, fine wiring has been difficult due to insufficiency in depth of focus in lithography, and more complicated processing technique and an increase in the number of processes have posed problems. Further, with a flattening method by polishing, the larger wafers forming semiconductor devices, the larger polishers used, so that more auxiliary materials such as abrasive grain and polishing pads are needed and much labor is required for replacing polishing pads. Further, these methods have disadvantages that the flatness of worked surfaces is degraded due to abrasion of polishing pads during working and a polishing efficiency becomes unstable. Also, these methods involve such a problem that working with a grindstone may cut wiring due to a wavy wafer. A method of manufacturing semiconductor devices of the invention is characterized in that the warp on the surface of a semiconductor device is corrected based on the that surface or the top surface of wiring and cuts of predetermined sizes are provided between a tool and the surface of the semiconductor device or the top surface of wiring based on the surface of the semiconductor device or the top surface of wiring to flatten layer insulation films.</p> |
