发明名称 Simulation based extractor of expected waveforms for gate-level power analysis tool
摘要 A simulation based power analysis tool extracts "expected" current waveforms from simulation results. These expected waveforms are then used to represent the power consumption for a corresponding circuit cell or groups of cells from which the waveform is derived. The expected waveform is a statistical representation of a current derived over a number of cycles. The expected waveform is derived by recording the starting time of each power arc with respect to a tool defined clock period. The width of the waveform is derived from the average current, propagation delay and intrinsic delay for arc. The expected waveform can take several forms depending on the accuracy required. Each form has a corresponding memory storage requirement. The starting time for each arc can be stored, which yields the most accurate "true" expected waveform. Alternatively, the minimum, maximum and average starting times for a given power arc can be stored from which a "weighted min-max" expected waveform can be constructed. This weighted expected waveform is less accurate than the "true" expected waveform but requires less memory to store the starting times. Alternatively, just the average starting time for the arc can be stored from which an "average" expected waveform can be formed. This form of the expected waveform requires the least amount of memory, but also the least accurate of the three.
申请公布号 US5835380(A) 申请公布日期 1998.11.10
申请号 US19960661888 申请日期 1996.06.11
申请人 LSI LOGIC CORPORATION 发明人 ROETHIG, WOLFGANG
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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