发明名称 |
Gate array architecture for multiplexer based circuits |
摘要 |
A gate array architecture adapted for circuits containing transmission gates. In one embodiment, the gate array architecture contains a base row having at least four alternating P- and N-channel transistor rows. The transistor rows are positioned between a first voltage and a second voltage rail. In another embodiment, the rows adjacent the first and second voltage rails have larger transistors to facilitate connection of the transistors as inverters or buffers. The rows more remotely positioned from the first and second voltage rails have smaller transistor sizes to facilitate connection of the transistors as transmission gates. The gate array architecture is particularly efficient when used to create serial multiplexer-based circuits.
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申请公布号 |
US5780883(A) |
申请公布日期 |
1998.07.14 |
申请号 |
US19970808249 |
申请日期 |
1997.02.28 |
申请人 |
TRANSLOGIC TECHNOLOGY, INC. |
发明人 |
TRAN, DZUNG JOSEPH;ACUFF, MARK WARREN |
分类号 |
H01L27/118;(IPC1-7):H01L27/10 |
主分类号 |
H01L27/118 |
代理机构 |
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主权项 |
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地址 |
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