Sub word line driving circuit and a semiconductor memory device using the same

摘要

A sub word line driving circuit for driving a sub word line is used for a semiconductor memory device having a hierarchical word line structure. The sub word line driving circuit includes two NMOS transistors for driving the sub word lines to reduce an area of overall memory device when being applied to a VLSI memory device of Gigabit class while there is no time loss caused by delay between driving signals heretofore required in a bootstrap process to involve high operating speed and to be favorable in a reliability aspect of the device.