| 发明名称 |
Data processor with circuit for regulating instruction throughput and method of operation |
| 摘要 |
<p>A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor. <IMAGE></p> |
| 申请公布号 |
EP0851336(A1) |
申请公布日期 |
1998.07.01 |
| 申请号 |
EP19970121563 |
申请日期 |
1997.12.08 |
| 申请人 |
MOTOROLA, INC. |
发明人 |
ALEXANDER, MICHAEL;KUTTANNA, BELLIAPPA |
| 分类号 |
G06F1/04;G06F1/20;G06F1/32;G06F9/30;G06F9/38;G06F15/78;(IPC1-7):G06F1/26 |
主分类号 |
G06F1/04 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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