发明名称 ELECTROPLATED INTERCONNECTION STRUCTURES ON INTEGRATED CIRCUIT CHIPS
摘要 <p>A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches.</p>
申请公布号 WO1998027585(A1) 申请公布日期 1998.06.25
申请号 US1996019592 申请日期 1996.12.16
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