| 摘要 |
<p>A run-length decoding apparatus, for use in a video signal decoding system, for decoding a run level coded video signal to provide decoded video signal comprises an address generator, receiving the run data, for generating a write address denoting a memory location for storing the level data, a counter, responsive to a clock signal, for generating a read address for sequentially addressing the memory locations from an upper most memory location to a lower most memory location, and memory, having a number of memory locations, for storing the level data based on the write address, and for generating the decoded data stored in the memory locations based on the read addresses to thereby provide the decoded video signal.</p> |
