发明名称 |
Graded LDD implant process for sub-half-micron MOS devices |
摘要 |
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
|
申请公布号 |
US5719424(A) |
申请公布日期 |
1998.02.17 |
申请号 |
US19950539385 |
申请日期 |
1995.10.05 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
AHMAD, AFTAB;DENNISON, CHARLES |
分类号 |
H01L21/28;H01L21/336;H01L21/8238;H01L29/10;H01L29/78;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|