| 摘要 |
PROBLEM TO BE SOLVED: To keep a high communication quality without increasing a circuit scale. SOLUTION: A self-running clock the frequency of which is comparatively low, one to four times with respect to the chip frequency of a received signal and the phase of which is asynchronous with respect to the chip phase of the received signal is used as a system clock. At this time, through a sampling timing by AD converters 106 and 107 are deviated from an ideal point at this time, the sample of the received signal of a deviated timing is interpolated by using a tap coefficient variable waveform forming a filter circuit 108 to approximate a value sampled with ideal timing. At the time of RAKE composing, a signal obtained by sampling the signals of all the paths with an optimum sampling timing is obtained without using an old main path tracking system or an independent tracking system. |
