发明名称 |
Pipelined processor with two tier prefetch buffer structure and method with bypass |
摘要 |
A method and apparatus for prefetching instructions in a pipelined processor including first and second prefetch buffers arranged in a two tier system. As instruction bytes are fetched from cache memory or external memory, those instruction bytes from memory for which there is space in the first level buffer are loaded therein, and, simultaneously, those valid instruction bytes in the second tier buffer for which there is room in the first tier buffer are also loaded into the first tier buffer. Those instruction bytes from memory for which there is not currently room in the first tier buffer are loaded into the second tier buffer. The second tier buffer is also used as a buffer for loading the instruction cache memory from the external memory.
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申请公布号 |
US5680564(A) |
申请公布日期 |
1997.10.21 |
申请号 |
US19950445569 |
申请日期 |
1995.05.26 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
DIVIVIER, ROBERT JAMES;NEMIROVSKY, MARIO |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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