| 摘要 |
<p>A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set. <IMAGE></p> |
