| 摘要 |
A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signals are superimposed upon the ladders by drivers which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC. |
