| 摘要 |
A parallel-to-serial data conversion circuit includes a control circuit receiving a load signal, a clock signal and high-order 4 bits of a parallel data of 8-bit PCM code excluding the MSB bit, for generating a first control signal and a second control signal, a 6-bit shift register receiving the first control signal, the second control signal, low-order 4 bits of the parallel data, a store signal and the clock signal, and a selector for selecting the output of the shift register on the basis of the MSB bit and the first control signal.
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