| 摘要 |
The method is for fabricating a DRAM having a stacked capacitor structure comprised by including the steps of forming an isolation oxide(5), a source and drain region(6), a bit line electrode(8') and a capacitor in sequence. The isolation oxide and the bit line electrode are formed in the patterns maintaining the same width and interval as a cell region to the boundary region between the cell and the periphery region and to some part of the periphery region extending to the boundary region.
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