| 摘要 |
<p>A method and apparatus for executing different sets of instructions that cause a processor (105) to perform different data type operations on different physical register file (615, 650) that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor (105) is provided that includes at least two physical register files (615, 650) -one for executing scalar data type operations (615) and the other for executing packed data type operations (650). In addition, the processor (105) includes a transition unit (600) that is configured to cause two physical register files (615, 650) to logically appear to software executing on the processor (105) as a single register file.</p> |
