发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS OPERATING METHOD, AND ELECTRONIC CIRCUIT DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To prevent the phenomenon of hot electron in a given memory cell when a charge accumulated in source and drain regions is reset after write and erase operation at a memory cell in a non-volatile memory. SOLUTION: A memory cell in a memory block MB is turned off just after write or erase operation is carried out in the given memory block of a flash memory. Then, potential of a main bit line BL is reduced to a grounding level, and switching MOSFET's Q1S and Q2s are turned on. As a result, a charge accumulated in a sub-source line SS and a sub-bit line BLS is each discharged to a grounding potential VSS or the main bit line BL.</p> |
申请公布号 |
JPH09153559(A) |
申请公布日期 |
1997.06.10 |
申请号 |
JP19950313798 |
申请日期 |
1995.12.01 |
申请人 |
HITACHI LTD;HITACHI VLSI ENG CORP |
发明人 |
TSUJIKAWA TETSUYA;TANAKA TOSHIHIRO;KANEMITSU MICHITARO;KATO MASATAKA;ADACHI TETSUO |
分类号 |
G11C17/00;G11C16/02;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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