发明名称 Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
摘要 A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c) . The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).
申请公布号 US5616959(A) 申请公布日期 1997.04.01
申请号 US19950473458 申请日期 1995.06.07
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 JENG, SHIN-PUU
分类号 H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L29/28;H01L23/54 主分类号 H01L21/768
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