发明名称 Processor unit for a parallel processor system discards a received packet when a reception buffer has insufficient space for storing the packet
摘要 A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.
申请公布号 US5594868(A) 申请公布日期 1997.01.14
申请号 US19950407853 申请日期 1995.03.21
申请人 HITACHI, LTD. 发明人 NAKAGOSHI, JUNJI;HIGUCHI, TATSUO;KATO, SHINICHI;ANDO, TOSHIMITSU;IWASAKI, MASAAKI
分类号 G06F12/14;G06F15/173;(IPC1-7):G06F13/14;G06F15/16;G06F15/163 主分类号 G06F12/14
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