BUS TRANSFERRING APPARATUS BETWEEN CPU AND PERIPHERAL

摘要

the first inverter inverting the phase of a bus grant signal outputted from a central processing unit(CPU); the first NAND gate performing a NAND operation of an address strobe signal(AS) from the CPU and the signal outputted from the first inverter; an OR gate performing an OR operation of the output of the first NAND gate and a bus request signal from a peripheral device; the second inverter inverting the phase of a bus grant signal from the peripheral device; a second NAND gate; the third NAND gate; a bus grant signal-generating means(100) generating the bus grant signal by comprising D flip-flops; a bus grant signal processing means(101) outputting the bus grant signal; and a bus grant acknowledge signal-generating means(102) including several bus grant acknowledge signal generators.