| 摘要 |
<p>A CMOS logic circuit which efficiently uses the relatively high power supply voltage of the system and consumes less electric power. The CMOS circuit is divided into a plurality of circuit blocks (5 and 6) and is formed on layers so as to divide the power supply voltage. A power supply voltage stabilizing unit (1) is provided for each layer and level converting circuits (7 and 8) for transferring signals. The power consumption of a system requiring a relatively high power supply voltage can be reduced without increasing the circuit scale by using a low-voltage CMOS logic circuit constituted of random logics, etc.</p> |
