| 摘要 |
<p>A variable-length decoding apparatus outputs symbol data corresponding to variable-length-coded data in units of a block having a predetermined magnitude, including a memory (21A, 21B) composed of a plurality of storage regions and for outputting information stored in a storage region designated by an input absolute address data, wherein each storage region corresponds to the absolute address data and stores relative address data, symbol data and a status signal representing whether or not a symbol is determined and indicative of the class of the determined symbol, an absolute address generator (23-25) for generating absolute address data in response to a control signal and the relative address data supplied from the memory (21A, 21B), and a controller (22) for generating the control signal in response to a start signal indicative of a start of each block having a predetermined magnitude, variable-length coded bit data and the status signal supplied from the memory. Thus, the control circuit can be designed in hardware compared with a conventional system using a barrel shifter, and a variable-length-coding table can be embodied by using a memory having a small capacity. <IMAGE></p> |
