| 摘要 |
<p>An NVRAM array (30) has a portion (31) associated with a drive line segment (DSL11). The drive line segment (DSL11) is coupled to a drive line (DL1) by a control transistor (32). The layout allows a conductive member (112) that is part of the drive line segment (DSL11) to be formed at about the same elevation as the memory capacitors (118). The layout further allows interconnects (136) for the drive lines (DL1, DL2) and bit lines (BL11, BL12, BL13, BL14) to be formed over the control and memory transistors (32, 34), as opposed to between the transistors. The process forms a small and reliable NVRAM device. <IMAGE></p> |
