发明名称 |
INTEGRATED CIRCUIT LAYOUT |
摘要 |
The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.
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申请公布号 |
WO9624904(A1) |
申请公布日期 |
1996.08.15 |
申请号 |
WO1996US01788 |
申请日期 |
1996.02.07 |
申请人 |
SILICON VALLEY RESEARCH, INC. |
发明人 |
DING, CHENG-LIANG;ZHU, JIABI, J. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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