| 摘要 |
PURPOSE: To provide an abnormal clock detection circuit capable of detecting the break and the pulse increase of an input clock signal. CONSTITUTION: An input clock signal A is inputted to an up/down counter circuit 4 through an input counter circuit 1 as a count-up signal E and has the phase and the frequency synchronized by a PLO circuit 2, and this synchronized signal C is inputted to the up/down counter circuit 4 through an output counter circuit 3 as a count-down signal F, and an alarm signal is outputted from an alarm circuit 5 based on the counted result. Since the signal is continuously counted down in the case of the break of the clock and is continuously counted up in the case of the increase of clock pulses in this constitution, both of the break of the clock and the increase of clock pulses can be detected. |
