| 摘要 |
<p>A ferroelectric memory includes a circuit for temporarily controlling a parasitic capacitance of a pair of data signal lines to an optimum value, when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained. <IMAGE></p> |
